Description of the Role:In this role as a Senior Lead Engineer (FPGA Verification Engineer, Actuation Systems) actively contribute towards Requirement-Based Testing (RBT) in FPGA verification using System Verilog and UVM methodology, in accordance to DO-254 process.Primary Responsibilities:1.Develop
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Senior Lead FPGA Verification Engineer - Actuation Systems M/F
Job Description:

Description of the Role:In this role as a Senior Lead Engineer (FPGA Verification Engineer, Actuation Systems) actively contribute towards Requirement-Based Testing (RBT) in FPGA verification using System Verilog and UVM methodology, in accordance to DO-254 process.Primary Responsibilities:1.Develop an effective suite of tests and test environments using System Verilog UVM, based tests to achieve predefined requirement verification goals.2.Develop test-plan, self-checking test-benches to meet the verification criteria and code coverage.3.Participate in requirement validation and requirement review.4.Protocols – PCIe, SPI, ARINC 429, Mil 1553, Image processing.5.Actively participate in a team environment and work independently with design teams to develop verification architecture, applications, comprehensive test plans and address issues.6.Verification environment development from scratch for block level and system level.7.Work closely with design team on design de-bugging, coverage gap analysis etc.8.Independently work towards functional and structural coverage closure for module and system level designs.9.Advanced skills in various programming languages such as System Verilog/UVM, PERL or any scripting language.10.Apply techniques and skills required to identify a root cause of a given issue and very good debugging skills.11.Technical guidance to the junior engineers on verification tasks.
Job Requirements:

Qualifications:•Bachelor's/Master's degree in Engineering (ECE or VLSI)•7-11 years of Industry experience with experience in development, integration & verification of ASIC/FPGA.•Hands on experience in developing SV-UVM verification environment from scratch.•Hands on experience with Questa or Modelsim or similar advanced simulation tools.•Hands on experience in DO-254 verification process.•Hands on experience in developing UVM verification environment from scratch from scratch with stimulus to achieve the code coverage, robust testing of the designs independently.•Exposure to test plan generation, test bench writing, simulation of designs.•Experience in RTL Design using VHDL, Complete FPGA development flow and FPGA verification using VHDL will be a plus.•Experience in DOORS/Jama will be a plus.Guide Junior engineers in the project execution and take the ownership of the deliverables.•Experience in leading team and reporting progress metrics.•Excellent oral and written communication skills
Company Details
Safran
2, Boulevard du General Martial Valin
Paris, Ile-De-France France, International 75724 International
www.safran-group.com
909 Open Jobs Available
Safran is a world leader in security. The company employs more than 8,600 people in 55 countries and in 2014 generated sales of more than 1.5 billion euros. Morpho's unique expertise lies in its ability to provide security solutions for the following...

Benefits:
TBD
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Job Info
Location
Paris, Ile-De-France France, International, France
Type
Permanent
Company Details
Safran
2, Boulevard du General Martial Valin
Paris, Ile-De-France France, International 75724 International
www.safran-group.com
909 Open Jobs Available
Safran is a world leader in security. The company employs more than 8,600 people in 55 countries and in 2014 generated sales of more than 1.5 billion euros. Morpho's unique expertise lies in its ability to provide security solutions for the following...

Benefits:
TBD

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